The present disclosure relates generally to integrated circuit design partitioning and prototyping.
In designing modern integrated circuits, a single design may include many transistor based modules such as microprocessors, memory devices and other functions in a single package. These functions are often developed in HDL (Hardware Description Language) design languages such as Verilog (Institute of Electrical and Electronic Engineers standard 1364) and VHDL (Very high speed integrated circuit Hardware Description Language). HDL source code is typically technology independent, that it is independent of the technology of a specific vendor such as of Field Programmable Gate Arrays (FPGA) or Applied Specific Integrated Circuits (ASIC). A logic synthesis and mapping operation is then performed to convert from HDL to a technology specific netlist, which can be used to create circuits in a specific vendor's technology.
In a process of validating the functionality of these integrated circuits, it is often required to prototype the entire integrated circuit in a Field Programmable Gate Array (FPGA) device before fabrication. Very often, however, these FPGA devices are not big enough to accommodate the entire integrated circuit design in a single FPGA device. In such cases, it is required to partition the entire integrated circuit design among multiple FPGA devices.
When a design requires multiple FPGAs, the design must be partitioned across the devices. Partitioning involves assigning portions of the design, i.e. logic functions and corresponding components, to each of the various devices.
A design can be thought of as a collection of hierarchies of logic blocks, with top level logic blocks being composed of lower level logic blocks. FIG. 1A is a diagram illustrating a partitioning of an example design 100 which may be expressed as a netlist, or other software-based circuit representation, as performed by a conventional synthesis tool. The netlist specifies the various logic blocks, or instances, of a design as well as the nets connecting those logic blocks. As shown, the design 100 can include the top level design 110. The design 100 further specifies five different logic hierarchies, in this example, corresponding to logic blocks 111, 112, 113, 114 and 115 respectively. Each logic block includes logic Under Test (LUT) (not shown) and each logic block may include sub-blocks (not shown). Partitioning typically assigns each logic block to a different FPGA, as shown in FIG. 1B. In this case the logic hierarchy represented by block 111 has been assigned to FPGA 121, the logic hierarchy represented by block 112 to FPGA 122, the logic hierarchy represented by block 113 to FPGA 123, the logic hierarchy represented by block 114 to FPGA 124, and the logic hierarchy represented by block 115 to FPGA 125. In addition, wire bus 131 connects I/O pins between FPGA 121 and 122, wire bus 132 connects I/O pins between FPGA 122 and 123, wire bus 133 connects I/O pins between FPGA 123 and 124, wire bus 134 connects I/O pins between FPGA 124 and 125 and wire bus 135 connects I/O pins between FPGA 125 and 121. Each one of these buses may be comprised of hundreds of wires, and typically there is a clock associated with each bus.
Conventional partitioning methods have limitations as to usability and the quality of the solutions that are achieved when partitioning across multiple devices. When partitioning, design constraints must be observed. One such constraint pertains to the number of connections that can be used between partitions, in this case individual FPGAs. Specifically, there cannot be more connections among the partitions than the total number of inputs and outputs (I/Os) available on the FPGAs concerned. When partitioning a design along logic hierarchy boundaries, as illustrated in FIGS. 1A and 1B, many connections required and the partitioning often violates this constraint. That is, the partitioning typically requires more I/Os than are available on the FPGA devices concerned. Violation of this constraint leads to an infeasible partitioning of the design. Many existing partitioning algorithms such as U.S. Pat. No. 7,844,930, Titled: “METHOD AND APPARATUS FOR CIRCUIT PARTITIONING AND TRACE ASSIGNMENT IN CIRCUIT DESIGN”, Filed: Jun. 12, 2007, overcome this problem by multiplexing the signals between blocks, hence, reducing the FPGA pins required. This method often results in reduced operating frequency and added complexity.
Another limitation of existing partitioning methods is that the wires that connects the inputs and output pins between the FPGAs have to be implemented in hardware. This implies that any change in the FPGA I/O signals will result in a new hardware implementation, such as a redesign of a printed circuit board (PCB) on which the FPGAs are mounted.
Still another limitation of existing partitioning methods is that timing of signals between the logic blocks in the partitioned design 120 may be substantially different from timing of signals between logic blocks in the original design 100, especially when the original design is implemented in single integrated circuit.
Accordingly, it would be beneficial to provide a method and system for partitioning a design across a plurality of devices in a manner that overcomes the deficiencies described above.